Testing and manufacture of integrated circuits generally includes testing and characterization of the circuit over an expected operational lifetime. Conventional testing includes generation of a digital representation of the circuit elements (commonly referred to as a netlist) and simulation of the netlist in expected operation conditions over the expected operational lifetime. Testing of circuits generates timing libraries that include data regarding performance of the circuit elements at the expected operational life (commonly referred to as aging data).
Current timing library generation relies on a characterization process that requires stressing and aging modeling of all circuit elements for each expected operational lifetime that is tested. To create a new aging library for a different expected operational lifetime, logic cell stressing is repeated, even when prior characterization processes have performed identical stress simulation of the circuit elements.